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MAX2769B
Universal GPS Receiver
AC ELECTRICAL CHARACTERISTICS* (continued)
(MAX2769B EV kit, V CC_ = 2.7V to 3.3V, T A = -40 N C to +85 N C, PGM = Ground. Registers are set to the default power-up states. LNA
input is driven from a 50 I source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set
to 51dB gain by serial-interface word GAININ = 111010. Maximum IF output load is not to exceed 10k I ||7.5pF on each pin. Typical
values are at V CC_ = 2.85V and T A = +25 N C, unless otherwise noted.) (Note 1)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
LNA2 INPUT
Power Gain
Noise Figure
13
1.14
dB
dB
Input IP3
Output Return Loss
Input Return Loss
(Note 5)
1
19
11
dBm
dB
dB
FREQUENCY SYNTHESIZER
LO Frequency Range
LO Tuning Gain
0.2V < V TUNE < (V CC_ - 0.3V)
1550
57
1610
MHz
MHz/V
Reference Input Frequency
Main Divider Ratio
Reference Divider Ratio
Charge-Pump Current
ICP = 0
ICP = 1
8
36
1
0.5
1
44
32,767
1023
MHz
—
—
mA
TCXO INPUT BUFFER/OUTPUT CLOCK BUFFER
Frequency Range
8
32
MHz
Output Logic-Level High (V OH )
Output Logic-Level Low (V OL )
Capacitive Slew Current
Output Load
Reference Input Level
With respect to ground, I OH = 10 F A (DC-coupled)
With respect to ground, I OL = 10 F A (DC-coupled)
Load = 10k W + 40pF, f CLKOUT = 32MHz
Sine wave
2
0.5
11
10||40
0.8
V
V
mA
k I ||pF
V P-P
Clock Output Multiply/Divide
Range
/4, /2, /1
(x2, max input frequency of 16MHz)
÷4
x2
—
ADC
ADC Differential Nonlinearity
ADC Integral Nonlinearity
AGC enabled, 3-bit output
AGC enabled, 3-bit output
Q 0.1
Q 0.1
LSB
LSB
Note 1: MAX2769B is production tested at T A = +25 N C and +85 N C. All min/max specifications are guaranteed by design and char-
acterization from -40 N C to +85 N C, unless otherwise noted. Default register settings are not production tested or guaran-
teed. User must program the registers upon power-up.
Note 2: Default, low-NF mode of the IC. LNA choice is gated by the ANT_FLAG signal. In the normal mode of operation without an
active antenna, LNA1 is active. If an active antenna is connected and ANT_FLAG switches to 1, LNA1 is automatically dis-
abled and LNA2 becomes active. PLL is in an integer-N mode with f COMP = f TCXO /16 = 1.023MHz and ICP = 0.5mA. The
complex IF filter is configured as a 5th-order Butterworth filter with a center frequency of 4MHz and bandwidth of 2.5MHz.
Output data is in a 2-bit sign/magnitude format at CMOS logic levels in the I channel only.
Note 3: The LNA output connects to the mixer input without a SAW filter between them.
Note 4: Two tones are located at 12MHz and 24MHz offset frequencies from the GPS center frequency of 1575.42MHz at -60dBm/
tone. Passive pole at the mixer output is programmed to be 13MHz.
Note 5: Measured from the LNA input to the LNA output. Two tones are located at 12MHz and 24MHz offset frequencies from the
GPS center frequency of 1575.42MHz at -60dBm per tone.
Maxim Integrated
* The parametric values (min, typ, max limits) shown in the Electrical Characteristics table supersede values quoted elsewhere in this data sheet.
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